preliminary 1-mbit (128k x 8) static ram cy7c109d cy7c1009d cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05468 rev. *c revised january 10, 2005 features ? pin- and function- compatible with cy7c109b/cy7c1009b ?high speed ?t aa = 10 ns ? low active power ?i cc = 60 ma @ 10 ns ? low cmos standby power ?i sb2 = 1.2 ma (?l? version only) ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 , ce 2 , and oe options ? available in pb-free packages functional description [1] the cy7c109d/cy7c1009d is a high-performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high chip enable (ce 2 ), an active low output enable (oe ), and tri-state drivers. writing to the device is accomplished by taking chip enable one (ce 1 ) and write enable (we ) inputs low and chip enable two (ce 2 ) input high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable one (ce 1 ) and output enable (oe ) low while forcing write enable (we ) and chip enable two (ce 2 ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c109d is available in standard 400-mil-wide soj and 32-pin tsop type i packages. the cy7c1009d is available in a 300-mil-wide soj pb-free package. the cy7c1009d and cy7c109d are functionally equivalent in all other respects. 14 15 logic block diagram pin configurations a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce 2 i/o 1 i/o 2 i/o 3 512 x 256 x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce 1 a a 16 a 9 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view soj 12 13 29 32 31 30 16 15 17 18 gnd a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 a 2 nc i/o 0 i/o 1 i/o 2 ce 1 oe a 10 i/o 3 a 1 a 0 a 11 ce 2 109d?2 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe tsop i top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 selection guide cy7c109d-10 cy7c1009d-10 cy7c109d-12 cy7c1009d-12 unit maximum access time 10 12 ns maximum operating current 60 50 ma maximum cmos standby current non-l com?l / ind?l 3 3 ma low power version 1.2 1.2 note: 1. for guidelines on sram system design, please refer to the ?syst em design guidelines? cypress application note, available on t he internet at www.cypress.com.
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 2 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc to relative gnd [2] .... ?0.5v to +7.0v dc voltage applied to outputs in high-z state [2] ....................................?0.5v to v cc + 0.5v dc input voltage [2] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ...... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 5v 10% industrial ? 40c to +85c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c109d-10 7c1009d-10 7c109d-12 7c1009d-12 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [2] ?0.5 0.8 ?0.5 0.8 v i ix input load current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 ?1 +1 a i os output short circuit current [3] v cc = max., v out = gnd ?300 ?300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 60 50 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce 1 > v ih or ce 2 < v il , v in > v ih or v in < v il , f = f max 10 10 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce 1 > v cc ? 0.3v, or ce 2 < 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 33ma l1.21.2ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 9pf c out output capacitance 8 pf thermal resistance [4] parameter description test conditions all-packages unit ja thermal resistance (junction to ambient) [4] still air, soldered on a 3 4.5 inch, two-layer printed circuit board tbd c/w jc thermal resistance (junction to case) [4] tbd c/w notes: 2. v il (min.) = ?2.0v and v ih (max) = v cc + 2v for pulse durations of less than 20 ns. 3. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 4. tested initially and after any design or process changes that may affect these parameters.
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 3 of 9 ac test loads and waveforms switching characteristics over the operating range [7] parameter description 7c109d-10 7c1009d-10 7c109d-12 7c1009d-12 unit min. max. min. max. read cycle t power [5] v cc (typical) to the first access 100 100 s t rc read cycle time 10 12 ns t aa address to data valid 10 12 ns t oha data hold from address change 3 3 ns t ace ce 1 low to data valid, ce 2 high to data valid 10 12 ns t doe oe low to data valid 5 6 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [8, 9] 56ns t lzce ce 1 low to low z, ce 2 high to low z [9] 33 ns t hzce ce 1 high to high z, ce 2 low to high z [8, 9] 56ns t pu ce 1 low to power-up, ce 2 high to power-up 00 ns t pd ce 1 high to power-down, ce 2 low to power-down 10 12 ns write cycle [10] t wc write cycle time [11] 10 12 ns t sce ce 1 low to write end, ce 2 high to write end 8 10 ns t aw address set-up to write end 7 10 ns notes: 5. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed 6. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s. 7. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 8. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. ce 1 and we must be low and ce 2 high to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to t he leading edge of the signal that terminates the write. 11. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (b) (c) 3 ns 3 ns output r1 480 ? r1 480 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th * capacitive load consists of all components of the test environment 30 pf* output z = 50 ? 50 ? 1.5v (a) 10-ns device 10-ns device 12 -ns devices
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 4 of 9 t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 7 10 ns t sd data set-up to write end 6 7 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [9] 33 ns t hzwe we low to high z [8, 9] 66ns switching characteristics over the operating range [7] parameter description 7c109d-10 7c1009d-10 7c109d-12 7c1009d-12 unit min. max. min. max. data retention characteristics over the operating range parameter description conditions min. max unit v dr v cc for data retention v cc = v dr = 2.0v, ce 1 > v cc ? 0.3v or ce 2 < 0.3v, v in > v cc ? 0.3v or v in < 0.3v 2.0 v i ccdr data retention current non-l, com?l / ind?l 3 ma l-version only 1.2 ma t cdr [4] chip deselect to data retention time 0 ns t r [6] operation recovery time t rc ns data retention waveform switching waveforms read cycle no. 1 [12, 13] notes: 12. device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 13. we is high for read cycle. 4.5v 4.5v ce v cc t cdr v dr > 2v data retention mode t r previous data valid data valid t rc t aa t oha address data out
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 5 of 9 read cycle no. 2 (oe controlled) [13, 14] write cycle no. 1 (ce 1 or ce 2 controlled) [15, 16] notes: 14. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. 15. data i/o is high impedance if oe = v ih . 16. if ce 1 goes high or ce 2 goes low simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 i cc i sb impedance address ce 2 data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce 1 address ce 2 we data i/o
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 6 of 9 write cycle no. 2 (we controlled, oe high during write) [15, 16] write cycle no. 3 (we controlled, oe low) [16] truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high z power-down standby (i sb ) x l x x high z power-down standby (i sb ) lhlhdata out read active (i cc ) l h x l data in write active (i cc ) l h h h high z selected, outputs disabled active (i cc ) note: 17. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 17 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t sce t wc t hzwe ce 1 address ce 2 we data i/o note 17
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 7 of 9 ordering information speed (ns) ordering code package name package type operating range 10 cy7c109d-10vxc v33 32-lead (400-mil) molded soj (pb-free) commercial cy7c1009d-10vxc v32 32-lead (300-mil) molded soj (pb-free) CY7C109D-10ZXC z32 32-lead tsop type i (pb-free) cy7c109d-10vxi v33 32-lead (400-mil) molded soj (pb-free) industrial cy7c1009d-10vxi v32 32-lead (300-mil) molded soj (pb-free) cy7c109d-10zxi z32 32-lead tsop type i (pb-free) 12 cy7c109d-12vxc v33 32-lead (400-mil) molded soj (pb-free) commercial cy7c1009d-12vxc v32 32-lead (300-mil) molded soj (pb-free) cy7c109d-12zxc z32 32-lead tsop type i (pb-free) cy7c109d-12vxi v33 32-lead (400-mil) molded soj (pb-free) industrial cy7c1009d-12vxi v32 32-lead (300-mil) molded soj (pb-free) cy7c109d-12zxi z32 32-lead tsop type i (pb-free) shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s. package diagrams 32-lead (300-mil) molded soj v32 51-85041-*a
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 8 of 9 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 32-lead (400-mil) molded soj v33 51-85033-*b 51-85056-*d 32-lead thin small outline package type i (8x20 mm) z32
preliminary cy7c109d cy7c1009d document #: 38-05468 rev. *c page 9 of 9 document history page document title: cy7c109d, cy7c1009d 1 -mbit (128k x 8) sram (preliminary) document number: 38-05468 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance information data sheet for c9 ipp *a 233722 see ecn rkf dc parameters are modified as per eros (spec # 01-2165) pb-free offering in ordering information *b 262950 see ecn rkf added data retention characteristics table added t power spec in switching characteristics table shaded ordering information *c 307596 see ecn rkf reduced speed bins to -10 and -12 ns
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